1. Field of Invention
This present invention generally relates to a driving circuit for an electro-optical device, and an electro-optical device, and electronic equipment using this electro-optical device as a display device.
2. Description of Related Art
An active matrix liquid crystal panel is known as an electro-optical device. This active matrix liquid crystal panel is constituted by filling and sealing the gap between a device substrate and an opposing substrate with liquid crystal serving as an electro-optical material. FIG. 10 is a block diagram illustrating the configuration of a liquid crystal panel 1 as an example of such an active matrix liquid crystal panel. In addition to this liquid crystal panel 1, FIG. 10 shows a timing signal generating circuit 2 and a γ-correction circuit 3, which are peripheral circuits of the liquid crystal panel 1. Each of these peripheral circuits is constituted by one or a plurality of semiconductor integrated circuits.
Before describing the configuration of the liquid crystal panel 1, these peripheral circuits are described hereinbelow. The timing signal generating circuit 2 is operative to generate various timing signals for controlling operation timing of each component of the liquid crystal panel 1. Among timing signals generated by this timing signal generating circuit 2, primary timing signals are a scanning-line selection pulse G, a data-line selection pulse DS, and selection signals SELA and SELB. Incidentally, one scanning-line selection pulse G is outputted in each frame time (or each vertical scanning period) from the timing signal generating circuit 2. Further, one data-line selection pulse DS is outputted during every horizontal scanning period in each frame time. Furthermore, the selection signals SELA and SELB are such that the signal levels of the signals SELA and SELB exclusively change in synchronization with the horizontal scanning period. That is, in the case that the signal level of the selection signal SELA is a high level in, for example, each odd-numbered horizontal scanning period, the signal level of the selection signal SELB is a high level in each even-numbered horizontal scanning period.
The γ-correction circuit 3 is operative to perform a γ-correction on analog image signals supplied to the liquid crystal panel 1. That is, each pixel (to be described later) of the liquid crystal panel 1 has a characteristic that the gradation level thereof nonlinearly changes according to a voltage applied thereto. Thus, a nonlinear conversion (namely, a γ-correction) represented by an inverse function of a function representing the nonlinear characteristic of each pixel is preliminarily performed on an analog image signal by this γ-correction circuit 3. Then, resultant signals are supplied to the liquid crystal panel 1, so that the gradation level of each pixel linearly changes according to the analog image signal.
Next, the liquid crystal panel 1 is described hereinafter. As described above, this liquid crystal panel 1 is constituted by filling and sealing the gap between the device substrate and the opposing substrate with liquid crystal serving as an electro-optical material. Incidentally, as illustrated in FIG. 10, M parallel scanning lines 11-i (i=1 to M) and N parallel data lines 12-j (j=1 to N), each intersecting with the scanning lines, are formed on the device substrate of the liquid crystal panel 1. Further, M×N pairs of a pixel Qij (i=1 to M, j=1 to N) and a switching transistor Tij (i=1 to M, j=1 to N) are formed at intersections between the scanning lines 11-i (i=1 to M) and the data lines 12-j (j=1 to N), respectively.
Each pixel Qij (i=1 to M, j=1 to N) consists of a pixel electrode provided on the device substrate, an opposing electrode provided on the opposing substrate, and a liquid crystal layer sandwiched between the pixel electrode and the opposing electrode. Each switching transistor Tij (i=1 to M, j=1 to N) is constituted by a TFT (Thin Film Transistor) formed on the device substrate.
Each data line 12-j is a wire for transmitting an analog image signal, according to which the gray scale levels of pixels are determined, and connected to the source of each of M switching transistors Tij (i=1 to M) of the same column number as the column number thereof. Further, each scanning line 11-i is a wire for transmitting selection voltage pulses, in response to which an analog image signal writing command is issued, and connected to the gate of each of N switching transistors Tij (j=1 to N) of the same row number as the row number thereof. The drain of the switching transistor Tij (i=1 to M, j=1 to N) is connected to the pixel electrode of the pixel Qij (i=1 to M, j=1 to N). Each of the switching transistors Tij (i=1 to M, j=1 to N) is conducted by applying a selection voltage to the gate thereof through the scanning line 11-i. An analog image signal provided on the data line 12-j, which is connected to the source of each of the switching transistors, is applied to the pixel electrode of the pixel Qij.
A scanning line driving circuit 13, a data line driving circuit 14, and N sampling circuits 15-j (j=1 to N) are formed on the device substrate of the liquid crystal panel 1, in addition to the aforementioned components.
The scanning line driving circuit 13 is operative to sequentially supply selection voltages Gi (i=1 to M) to the scanning lines 11-i (i=1 to M) during each horizontal scanning period in one frame time (or one vertical scanning period) under the control of the timing signal generating circuit 2. This scanning line driving circuit 13 can be constituted by a shift register adapted to serially shift, for example, the scanning selection pulse G. In the case of using this shift register, this scanning line driving circuit 13 should be configured so that a pulse obtained from each stage of this shift register is supplied to the corresponding scanning line 11-i (i=1 to M).
The data line driving circuit 14 is operative to sequentially output N sampling pulses SPj (j=1 to N) when the selection voltage is outputted to each of the scanning lines. This data line driving circuit 14 can be constituted by, for instance, a shift register adapted to sequentially shift the data-line selection pulses DS. In the case of using this shift register, the data line driving circuit 14 should be configured so that the sampling pulses SPj (j=1 to N) are extracted from the stages of this shift register.
The sampling circuits 15-j (j=1 to N) are provided correspondingly to the data lines 12-j (j=1 to N), respectively. The selection signals SELA and SELB are supplied to each of the sampling circuits 15-j (j=1 to N). Furthermore, each of the sampling circuits 15-j (j=1 to N) is supplied with a corresponding one of sampling pulses SPj (j=1 to N) in each horizontal scanning period.
Each of the sampling circuits 15-j (j=1 to N) is constituted by connecting analog switches SA-j, SB-j, SC-j, SD-j, and SS-j, voltage follower buffers BUFA-j and BUFB-j and capacitors CA-j and CB-j to one another, as illustrated in this figure.
Each of the analog switches SA-j, . . . is constituted by a TFT provided on the device substrate. Incidentally, the analog switch SS-j is conducted by being supplied with a high-level sampling pulse SPj. Further, the analog switch SA-j is conducted only when the selection signal SELA is at a high level. Moreover, the analog switch SB-j is conducted only when the selection signal SELA is at a low level. Furthermore, the analog switch SC-j is conducted only when the selection signal SELB is at a high level. Additionally, the analog switch SD-j is conducted only when the selection signal SELB is at a low level.
FIG. 11 is a timing chart illustrating an operation of the aforementioned liquid crystal panel. Hereinafter, an operation of the conventional active matrix liquid crystal display device is described hereunder with reference to this timing chart.
As illustrated in FIG. 11, in each frame time, selection voltage pulses G1, G2, . . . are serially and respectively outputted during horizontal scanning periods. Furthermore, the levels of the selection signals SELA and SELB are exclusively changed in synchronization with the horizontal scanning period.
In an example illustrated in FIG. 11, in a first horizontal scanning period in which the selection voltage pulse G1 is outputted, the selection signal SELA is at a high level, while the selection signal SELB is at a low level. Thus, among the sampling circuits 15-j (j=1 to N), the analog switches SA-j and SD-j are conducted, while the analog switches SB-j and SC-j are in a non-conducting condition.
In this state, when the sampling pulses SPj (j=1 to N) are serially outputted from the data line driving circuit 14, the analog switches SS-j of the sampling circuits 15-j (j=1 to N) are serially conducted. Then, analog image signals corresponding to the pixels, which are serially outputted from the γ-correction circuit 3, are sequentially applied to the capacitors CA-j (j=1 to N) through the analog switches SS-j (j=1 to N) and SA-j (j=1 to N). Subsequently, the applied analog image signals are held by the capacitors.
During this time, voltage signals written to the capacitors CB-j (j=1 to N) of the sampling circuits 15-j (j=1 to N) in the immediately preceding horizontal scanning period are outputted to the data lines 12-j (j=1 to N) through the analog switches SD-j (j=1 to N). The voltage outputted to each of the data lines 12-j (j=1 to N) is applied to the pixels Q1j (j=1 to N) of the first row through the switching transistors T1j (j=1 to N) when the selection voltage pulse G1 is at the high level. In FIG. 11, hatched parts of the voltage signals outputted from the capacitors CB-j (j=1 to N) to the data lines 12-j (j=1 to N) are applied to the pixel electrodes of the pixels Q1j (j=1 to N).
Subsequently, in a second horizontal scanning period in which the selection voltage pulse G2 is outputted, the selection signal SELA is at the low level, while the selection signal SELB is at the high level. Thus, in the sampling circuits 15-j (j=1 to N), the analog switches SB-j and SC-j are conducted, while the analog switches SA-j and SD-j are in a non-conducting condition.
In this state, when the sampling pulses SPj (j=1 to N) are serially outputted from the data line driving circuit 14, the analog switches SS-j of the sampling circuits 15-j (j=1 to N) are serially conducted. Then, analog image signals corresponding to the pixels, which are serially outputted from the γ-correction circuit 3, are sequentially applied to the capacitors CB-j (j=1 to N) through the analog switches SS-j (j=1 to N) and SB-j (j=1 to N). Subsequently, the applied analog image signals are held by these capacitors.
During this, voltage signals written to the capacitors CA-j (j=1 to N) of the sampling circuits 15-j (j=1 to N) in the immediately preceding horizontal scanning period are outputted to the data lines 12-j (j=1 to N) through the analog switches SC-j (j=1 to N). The voltage outputted to each of the data lines 12-j (j=1 to N) is applied to the pixels Q2j (j=1 to N) of the second row through the switching transistors T2j (j=1 to N) when the selection voltage pulse G2 is at the high level. In FIG. 11, hatched parts of the voltage signals outputted from the capacitors CA-j (j=1 to N) to the data lines 12-j (j=1 to N) are applied to the pixel electrodes of the pixels Q2j (j=1 to N).
In the subsequent horizontal scanning periods, similar operations are repeated. Thus, the analog image signals respectively corresponding to all pixels of one screen are applied to the pixel electrodes of the pixels Qij (i=1 to M, j=1 to N) of the liquid crystal panel 1.
In each of the pixels Qij (i=1 to M, j=1 to N), the alignment of liquid crystal molecules between the pixel electrode and the opposing electrode changes according to the voltage applied thereto, so that the transmittance of this pixel changes. Consequently, each of the pixels is displayed at a gradation level corresponding to the level of the corresponding analog image signal.